Home
|
About
|
Membership
|
Register
|
Contact Us
|
Site Links
|
Site Map
|
Login
Record Details
«
New Search
Brief Record
Full Record
MARC Record
Bibliographic Data
Control Number
UPD-00000178428
Date and Time of Latest Transaction
20090716221757.0
General Information
080209s1993 us 000 eng
International Standard Book Number
0792392817
Cataloging Source
DENG
Language Code
eng
Local Call Number
TK 7871.99 M44 S26
Added Entry - Personal Name
Kang, Sung-Mo (Steve)
Main Entry - Personal Name
Sapatnekar, Sachin S.
Title Statement
Design automation for timing-driven layout synthesis / Sachin S. Sapatnekar, Sung-Mo (Steve) Kang
Physical Description
xix, 269 p
Subject Added Entry - Topical Term
Computer-aided design
Integrated circuits -- Very large scale integration -- Design and construction -- Data processing
Metal oxide semiconductors, Complementary -- Design and construction -- Data processing
Collection Category
FO
Format
Monograph
Location
UP DENG-II TK 7871.99 M44 S26 UDEGB0034666 Regular Circulation E-ESEP-3746
Textual Physical Form Designator
Book
Physical Location
University of the Philippines
Diliman: College of Engineering Library II
TK 7871.99 M44 S26
Digital Copy
Not Available
Add to Book Cart
|
Download MARC
Online Catalog
Basic Search
Advanced Search
Browse Subjects
Book Cart
Text Size:
S
-
M
-
L
Home
|
About
|
Membership
|
Register
|
Contact Us
|
Site Links
|
Site Map
|
Login
Copyright © 2004-2025. Philippine eLib Project
Host: U.P. Diliman University Library