Search Results       Your search for [author]Kong, Jeong-Taek, 1959- returned 1 record.           Digital timing macromodeling for VLSI design verification. by Kong, Jeong-Taek, 1959-; Boston: Kluwer Academic, 1995. Subject: Integrated circuits -- Very large scale integration -- Design and construction -- Data processing; Integrated circuits -- Verification -- Data processing; Computer-aided design.          Add to Book Cart Relevance: 42.62%